1. Field of the Invention
This invention generally pertains to the field of level shifter circuits, and more particularly, to level shifter circuits with low leakage current.
2. Description of the Related Art
FIG. 1 is a block diagram of an arrangement of two circuits 110, 120 that operate with different supply voltage levels. The first circuit 110 operates between voltage levels Vcc and Vss, and outputs a signal VSIG that also has voltage levels between Vcc and Vss. The second circuit 120, which receives the signal VSIG, operates between two different voltage levels VPP and VBB (e.g., VPP>Vcc and VBB<Vss).
If the circuits 110 and 120 are connected directly together as shown in FIG. 1, then one or both circuits will exhibit an undesirably high leakage current when active. This in turn increases the power consumption of the arrangement, and any electronic device or system (e.g., a memory device) including the arrangement.
Accordingly, to address this problem, level shifters are often interposed between two circuits that operate with different supply voltage levels. In the example of FIG. 1, both a high level and low level shifter are needed between the output of the first circuit 110 and the input of the second circuit 120.
FIG. 2A shows a conventional high level shifter 200. The level shifter 200 receives an input signal IN which has two voltage levels Vcc and Vss and outputs complementary first and second output signals OUT and OUTB having voltage levels VPP and Vss, where VPP>Vcc.
The voltage shifter 200 includes pull-up transistors 205 and 215, pull-down transistors 210 and 220, and inverter 250. Explanation of the various connections between the transistors 205, 210, 215 and 220 and inverter 250 is omitted for brevity as those connections can be easily seen and understood from inspection of FIG. 2A.
FIG. 2B shows the input and output signals IN and OUT of the high level shifter 200. Operation of the high level shifter 200 is explained with respect to FIG. 2B.
When the input signal IN has the low voltage level Vss, then the pull-down transistor 210 is turned off, while the pull-down transistor 220 is turned on, pulling the output signal OUT low, approximately down to Vss. The output signal OUT going low, in turn, turns-on the pull-up transistor 205, pulling the inverted output signal OUTB high, approximately up to VPP. Meanwhile, the inverted output signal OUTB going high, in turn, turns-off the pull-up-transistor 215, insuring that the output signal OUT remains low.
On the other hand, when the input signal IN has the high voltage level Vcc, then the pull-down transistor 210 is turned on, pulling the inverted output signal OUTB low, approximately down to Vss, while the pull-down transistor 220 is turned off. The inverted output signal OUTB going low, in turn, turns-on the pull-up transistor 215, pulling the output signal OUT high, approximately up to VPP. Meanwhile, the output signal OUT going high, in turn, turns-off the pull-up-transistor 205, insuring that the inverted output signal OUTB remains low.
FIG. 3A shows a conventional low level shifter 300. The level shifter 300 receives an input signal IN which has two voltage levels Vcc and Vss and outputs complementary first and second output signals OUT and OUTB having voltage levels Vcc and VBB, where Vss>VBB. FIG. 3B shows the input and output signals IN and OUT of the low level shifter 300.
The connections and operation of the conventional low level shifter 300 are similar to those of the high level shifter 200 of FIG. 2A, and so for brevity will not be described in detail herein.
Unfortunately, the level shifters 200 and 300 suffer from an undesirably high leakage current. For example, in FIG. 2 when the input signal IN has the low voltage level Vss, then the Vgs of pull-down transistor 210 is 0 volts. However, even when Vgs=0 volts, a small leakage current may flow through the pull-down transistor 210.
U.S. Pat. No. 6,385,099 discloses another level shifter that exhibits reduced leakage current when in the standby mode. FIG. 4 shows an embodiment of the level shifter 300 disclosed in U.S. Pat. No. 6,385,099. The level shifter 400 is similar to the level shifter 200, with the difference being that the source of pull-down transistor 210 in FIG. 2 is tied to Vss, while the source of pull-down transistor 410 in FIG. 4 is tied to the output of inverter 450. Therefore, in the standby mode, when the input signal IN has the low voltage level Vss, the source of pull-down transistor 410 is tied to a higher voltage (e.g., VPP). Accordingly, the Vgs of pull-down transistor 410 is substantially negative, thereby substantially reducing the leakage current flowing therethrough in the standby mode, compared to the pull-down transistor 210 of FIG. 2.
However, the level shifter 400 still exhibits an undesirably high leakage current in the active mode.
Accordingly, it would be desirable to provide a level shifter that exhibits low leakage current in both a standby mode and an active mode. It would also be desirable to provide a level shifter with low leakage current that shifts both the high and low voltage levels.